The present invention relates to semiconductor device structures. More particularly, embodiments of the present invention provides methods for forming through-silicon-via or through-substrate via (TSV) interconnect structures.
Since the advent of semiconductor technology, integration of various electronic components continues to improve. Enhanced integration has come mainly from the minimum feature size decreases, so that more components can be formed in a given area. However, this integration is two-dimensional, and a significant improvement in two-dimensional photolithography technology for manufacturing integrated circuits plays an important role. But there are problems of two-dimensional integrated circuit density limit.
To further increase the circuit density, three-dimensional vertical stacking techniques are used vertically stack multilayer IC components to shorten the average line length to save space. Each edge portion of the plurality of lead pins of the chip may be needed, and according to the need to use pins, the chip will need to be interconnected using the connecting wires, or the use of these pins are connected through the chip to the circuit board. But in the three-dimensional interconnect stack, the connection between the chips are more complex, unwieldy, and can lead to circuit increasing the volume of circuit board.
For this reason, a TSV (through-silicon-via) techniques have been proposed for three-dimensional ICs. The through-silicon vias are formed through the silicon wafer to form vertical connections between different wafers.